Skills required:
• Hands-on Experience in Full Chip Layout.
• Must have experience on Technode’s 7nm and below.
• Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification Tool (Assura or Hercules is a plus).
• Performing various kinds of layouts, implementations from top-level, floor planning down to complex block level layouts.
• Knowledge of different layout techniques, understanding of critical constraints in the circuit to be taken care of in layout.
• Should have good knowledge in CMOS/BiCMOS/SOI/FinFETLayout concepts, Device Physics, and Fabrication concepts.
• Perl and Shell Scripting (Preferred).
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