What will you be doing in this role? (Responsibilities)
As a Physical Design Engineer in the team, you will be working independently on the entire flow from RTL to GDSII.
Understand the design, clock architecture, reset architecture, DFT architecture and influence them as per Physical Design needs.
Responsible for Place & Route, Reliability and Physical verification, Reliability closure
Methodologies to keep the PD cycle efficient and predictable.
Techniques to reduce Power and Area to make the device competitive
Techniques used in automotive designs.
Ability to interface with Fab and Qualification teams.
What do we expect from you? (Minimum Qualifications)
Bachelor or Master’s degree in Electrical/Electronics Engineering.
1-2 years of Physical Design experience
Good understanding and mastery in PD flow using Cadence tools and basic TCL scripting.
Knowledge of design requirements and guidelines for automotive applications and associated analog DFT hooks is a desirable
High speed (up to 2Ghz) design closure experience
Experience/Understanding of Backend flows like Synthesis, Floorplan & Powerplan, Placement, Clock Tree Synthesis, Route, STA, Reliability & Physical verification closure.
Preferred Skills/ Experience
Experienced with IC design and full development cycle from definition through release to production.
Effective communication skills to interact with all stakeholders.
Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team
Must be highly focused and remain committed to obtaining closure on project goals